IC Layout Engineer

The role

Lumilens builds optical interconnect for AI data centers: silicon photonics, mixed-signal ICs, electrical-optical interposers, and the systems around them. Our silicon ships in production AI clusters today, and volume is climbing fast.

You will own layout for our electronic ICs (EICs) and photonic ICs (PICs). These are high-speed analog blocks where the layout is the design: a parasitic you did not anticipate, a return path you did not control, or a current density you did not check will cost the part its margin.

You will also support photonic IC (PIC) layout as our schedule demands, and own the integration of electronic and photonic dies as they come together.

Singapore puts you close to the assembly and test supply chain we depend on, working alongside a senior layout engineer and partnering with design teams across the US, India, and Singapore.

Responsibilities

• Own layout for assigned analog and mixed-signal blocks: device placement, matching and symmetry, shielding, guard rings, and routing, from floorplan through to clean sign-off.

• Execute parasitic-aware layout — build to the constraints given by designers, run extraction, and take the results back to them when the layout says something the schematic did not expect.

• Route high-speed signal paths with attention to impedance, coupling, and return paths, and lay out passive and electromagnetic structures under senior direction.

• Run and close DRC, LVS, antenna, and density checks on your blocks, and support electromigration and IR drop analysis.

• Support top-level assembly and chip finishing activities through tape out.

• Support PIC layout as the need arises, including waveguide and curvilinear structures.

• Lay out photonic components and waveguide routing — bends, tapers, couplers, grating and edge couplers, and modulator and photodetector electrodes — from designer-provided geometry, honoring minimum bend radius, waveguide spacing, and phase- and length-matching constraints.

• Run photonics-specific verification: curvilinear DRC against the photonics PDK, waveguide connectivity and port checks, LVS on custom photonic cells, and clean GDS stream-out for tape out.

• Build the scripts and reusable structures that make the layout team faster.

Qualifications

• Diploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands-on layout experience.