IC Layout Engineer

The role

Lumilens builds optical interconnect for AI data centers: silicon photonics, mixed-signal ICs, electrical-optical interposers, and the systems around them. Our silicon ships in production AI clusters today, and volume is climbing fast.

You will own layout for our electronic ICs (EICs) and photonic ICs (PICs). These are high-speed analog blocks where the layout is the design: a parasitic you did not anticipate, a return path you did not control, or a current density you did not check will cost the part its margin.

You will also support photonic IC (PIC) layout as our schedule demands, and own the integration of electronic and photonic dies as they come together.

Singapore puts you close to the assembly and test supply chain we depend on, partnering with design teams across the US, India, and Singapore. You will be the senior layout voice on the ground here.

Responsibilities

Block and top-level layout

• Own floorplan and layout for high-speed analog and mixed-signal blocks: TIAs, drivers, SerDes front ends, PLL and clocking, references and bias.

• Execute device-level matching and symmetry — common-centroid, dummies, shielding, guard rings, substrate isolation — to the level these circuits actually require.

• Route high-speed signal paths with control over impedance, coupling, and return paths. Lay out passive and electromagnetic structures (inductors, transformers, transmission lines) and work with designers through EM simulation.

• Own chip finishing: pad ring, bump and pillar maps, seal ring, density fill, and top-level assembly through tape out.

Physical closure

• Drive parasitic-aware layout: iterate with designers on extraction results and close the loop between what the schematic assumed and what the layout delivers.

• Own electromigration and IR drop closure — current density, power grid construction, and the analysis that proves it holds at temperature and lifetime.

• Take blocks through DRC, LVS, antenna, DFM, and ESD and latch-up checks to sign-off.

Photonics and integration

• Support PIC layout as the need arises: waveguide and curvilinear structures, and the design rules that come with a photonics platform.

• Own layout of photonic blocks: waveguide routing under bend-radius, spacing, and length-matching constraints; modulator (MZM, ring) and photodetector electrode layout co-optimized with the RF drive path; and grating and edge coupler placement against fiber-attach and packaging constraints.