Member of Technical Staff
Posted 17 Aug 2026
Advertised as “Member of Technical Staff - Formal Verification”
BranchFactor Summary
The original posting with the fluff stripped out
- Management level
- Individual contributor
- Employment
- On-Site
- Contract
- Full-time
No salary listed for this role.
Field of studyComputer Engineering, Computer Science, Electrical Engineering (or related)
Study levelBachelor's or higher
About Architect Labs
Architect is a frontier AI lab for specialized computing systems. We partner with AI labs, clouds / neoclouds, quant firms, physical AI companies, fabless companies, IP providers, system companies and advanced fabs to tape-out custom hardware co-designed for their next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team has led research teams at nearly every frontier AI lab and led chip programs for some of the most complex SoCs in the world.
What You'll Do
As a Member of Technical Staff - Formal Verification Engineer at Architect Labs, you'll own formal verification of the AI-generated chip design artifacts, from early specifications through tape-out. You'll turn design intent into assertions, build formal environments, and work directly with designers to formally verify complex designs.
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Develop and execute formal verification plans using AI for hardware blocks and subsystems. Identify critical properties, define the scope of verification, and establish clear criteria for closure.
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Work with the AI researchers to build Spec to SVA flows including test plans, formal testbenches that capture functional requirements, interface protocols, and corner cases. Review assumptions against the specification and the environment the block will operate in.
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Drive proofs to completion using abstraction, decomposition, invariants, and appropriate solver strategies. Diagnose inconclusive results and make difficult designs tractable without hiding the behavior you need to verify.
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Debug counterexamples, isolate root causes, and work with RTL designers to resolve issues. Turn bugs into regression properties that catch the same failure in future revisions.
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Assess verification completeness through coverage analysis, reachability checks, vacuity checks, and assumption reviews. Document what has been proven, what remains open, and where simulation or other methods are needed.
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Build reusable verification components and automate formal regressions, result tracking, and failure triage. Work with our formal methods and ML teams to bring these checks into the AI-driven design flow.
What We'd Like to See
Qualifications & Skills:
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Degree: BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.