RFIC Design Engineer

Company Description

WD is building the infrastructure behind the AI-driven data economy.

As AI scales, so does data. Every interaction, every model, every system generates data that must be stored, managed, and made accessible over time. That’s where we come in.

We combine deep engineering expertise with global-scale manufacturing to deliver the storage systems that make AI possible, powering hyperscale data centers, cloud platforms, and enterprise infrastructure worldwide.

This isn’t theoretical work. It’s real systems, at real scale, people solving some of the hardest challenges in technology today.

We’re looking for people who want to build, solve, and operate at that level.

Join us and let’s shape the future of data.

Job Description

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Designer will be responsible for the design of high performance analog and mixed-signal circuit blocks.
• Responsibilities include transistor level, block level and module level circuit architecture, design, simulation, optimization, layout supervision, layout verification, preparation of test plan for the test group, product characterization, reliability and yield assessment and modeling, simulation to bench and bench to test correlation, bench evaluation both at silicon level and at applications level, and documentation.
• Job responsibilities require ability to communicate at all levels and with cross functional groups.
• Candidate must have good verbal and written communications skills and demonstrated track record of circuit innovation, must be a team player, be adaptable, and accept constructive criticism

Qualifications

• Must have hands-on design and development experience in analog and mixed-signal integrated circuit
• Must have experience in at least one preferably multiple area of full CMOS circuit design and development in:
  • Amplifiers – operational, instrumentation, wide-bandwidth etc.
  • PMIC – Linear and switched regulators, Low-drop out regulators etc.
  • Data converters – ADC, DAC, Flash and SAR type
• Must have experience in 40nm and below CMOS technology
• Must have a demonstrable track record of successful design releases and mass production
• Must have thorough knowledge of industry standard EDA tools (Cadence, Mentor, Siemens, Ansys etc.)
• Experience with analog layout techniques of mismatch reduction, gradient suppression, parasitic effects minimization
• Experience with floor planning, block level routing and top level chip routing