ATE Test Engineer

About us

We see the semiconductor industry as a realm of possibility. We see opportunity. We see the profound impact that our graphene solutions will have in transforming the industry. We invite you to join us in driving change with our fundamentally human-centered approach, uniting bright minds around a shared vision. The vision is: Prove to everybody that you can make a fundamental change. Prove with your knowledge and skills how things can be done differently. Together, we can change the paradigm of how the world connects

About our technology

The semiconductor industry’s growing demand for more powerful chips with higher bandwidth and lower power finds its solution in our technology. We connect chips to high-throughput, low-delay computing networks. The key lies in harnessing the physical properties of graphene to combine electronic computing with photonic communication, allowing countless chips to interact almost as if they were one. Our graphene photonic innovation increases computing power and efficiency to a new order of magnitude

In short, we connect chips to create powerful and energy-efficient networks, overcoming connectivity limitations in the semiconductor industry. We deliver the graphene solution

 

The Role

As a Senior Automated Test Equipment (ATE) Test Engineer, you will own the bring-up and operation of our high-volume 300 mm wafer test infrastructure for electronic-photonic integrated circuits. On a daily basis, you will set up and qualify ATE test cells, develop and debug test programs for DC, RF, and electro-optical device characterization, and drive probe card design with vendors. You will analyze wafer-level data to make pass/fail calls and share insights with design and process teams, helping us scale from engineering characterization to high-volume production.

To join our team, you should be excited to:

• Set up, qualify, and calibrate ATE test cells, ensuring readiness for high-volume wafer testing.

• Develop and debug automated test programs for DC, RF, optical, and electro-optical device characterization, including new measurement methods.

• Own probe card specifications, design, qualification, and integration, alongside associated interface hardware, in collaboration with vendors.

• Collaborate across teams to define comprehensive measurement plans and contribute to design-for-test (DFT) implementation.

• Collect, analyze, and report wafer-level measurement data to determine pass/fail outcomes and support yield monitoring, reliability testing, and failure analysis.