FPGA Engineer

Req ID: 140067 
Region: Asia 
Country: China 
State/Province: Shanghai 
City:  Shanghai 

Job Description:

The FPGA/CPLD engineer will play a key role in designing, implementing, and validating FPGA/CPLD-based solutions for data center server, storage, and switching platforms.

The role involves defining system FPGA/CPLD architecture, technical proposal and part selection, writing RTL code, running simulations, FPGA/CPLD schematic and PCB design review and validating designs on hardware. You will be responsible for optimizing designs to meet system requirements and working closely with hardware and software engineers to ensure full integration.

This position works in a cross-functional team with designers, customers, and project leaders to ensure robust and high-quality product development. The FPGA/CPLD engineer will also help improve designs based on feedback from areas such as manufacturing, reliability, and testing.

Job Responsibilities:

• Work closely with system architecture, hardware designer and software designer to understand/define the architecture requirements
• Create the design specification, test plans, and reports to ensure design traceability.
• Cooperate with hardware engineer on the logic part schematic design /review etc.
• On-time delivery of the RTL design and module-level verification and test case definition
• Perform pre-synthesis and post-synthesis simulation and validation.
• Drive the entire back-end design flow including design constraints, floor-plan and timing analysis.  
• Lead debugging and failure analysis efforts during FPGA/CPLD on-board validation.
• Collaborate with peers including different function team to ensure the successful delivery of high-performance systems
• As a mentor to junior engineers, provide training and technical guidance.
• Provide accurate and timely project schedule estimates, meet project milestone schedule

Job Requirement:

• Bachelors or master's in computer science, Communication and System Engineering, Electrical Engineering or related fields
• BSEE with 10+ years of FPGA/CPLD experience or MSEE with 5+ years of experience, familiar with Xilinx and Intel(Altera)FPGA and Lattice CPLD/FPGA etc.
• In depth knowledge with Verilog, System Verilog, RTL design, FPGA/CPLD design, and FPGA/CPLD design tools (eg. ISE, Vivado, Quartuse-II, Diamond, Modelsim etc.)
• In depth knowledge with high speed serial protocols such as PCIe/USB/Ethernet/DDR/LVDS;