Hardware Design Engineer

Req ID: 139686 
Remote Position: No
Region: Asia 
Country: Taiwan 
State/Province: Taiwan 
City:  Taipei 

General Overview

Functional Area:  Engineering        
Career Stream:  Design Engineering Hardware    
SAP Short Name:  SLE-ENG-DHW
Job Level:  Level 09
IC/MGR: Individual Contributor        
Direct/Indirect Indicator:  Indirect    

Summary

The FPGA/CPLD engineer will play a key role in designin g, implementing, and validating
FPGA/CPLD based solutions for data center server, storage, and switching platforms.
The role involves defining system FPGA /CPLD architecture, technical proposal and part selection,
writing RTL code, running simulations, FPGA/CPLD schematic and PCB design review a nd validating
designs on hardware. You will be responsible for optimizing designs to meet system requirements
and working closely with hardware and software engineers to ensure full integration.
This position works in a cross functional team with designer s, customers, and project leaders to
ensure robust and high quality product development. The FPGA /CPLD e ngineer will also help
improve designs based on feedback from areas such as manufacturing, reliability, and testing.

Detailed Description

Performs tasks such as, but not limited to, the following:

• Work closely with system architecture , hardware designer and software designer to
understand/define the architecture requirements
• Create the design specification test plans, and reports to ensure design traceability.
• Cooperate with hardware engineer on the logic par t schematic design /review etc.
• On time delivery of the RTL design and module level verifica tion and test case definition
• Perform pre synthesis and post synthesis simulation and validation.
• Drive the entire back end design flow including design constrain ts, floor plan and timing
analysis.
• Lead debugging and failure analysis efforts during FPGA /CPLD on board validation.
• Collaborate with peers inc luding different function team to ensure the successful delivery
of high performance systems
• As a mentor to junior engineers, provide training and technical guidance.
• Provide accurate and timely project schedule estimates , meet project milestone schedule

• Bachelors or Masters in Computer Science, Communication and System Engineering, Electrical Engineering or related fields • BSEE with 10 + years o f FPGA/CPLD experience or MSEE with 5 + years of familiar with Xilinx and Intel(Altera)FPGA and Lattice CPLD/FPGA etc. • In depth knowledge with Verilog, System Verilog, RTL design, FP GA /CPLD design, and FPGA /CPLD design tools ( eg. ISE, Vivado, Quartuse II, Diamond, Modelsim etc.etc.) • In depth knowledge with high speed serial protocols such as PCIe/ USB/ Ethernet/DDR/LVDS; • Familiar with SPI , eSPI , I2C , UART , LPC , MDIO etc low speed interface • amiliar with UVM constrained random coverage driven concepts, assertion based verification and f unctional coverage techniques • Proficient in und erstanding hardware schematics and PCB designs for FPGA/CPLD pinout constraints and on board validation.