Member of Technical Staff
Posted 17 Dec 2025
Advertised as “Member of Technical Staff, ASIC Design”
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 5+ yrs
- Management level
- People management
- Employment
- On-Site
- Contract
- Full-time
- Visa sponsorship
- Offered
No salary listed for this role.
Field of studyComputer Engineering, Electrical Engineering (or related)
Study levelBachelor's or higher
Field of studyComputer Engineering, Electrical Engineering (or related)
Study levelDoctorate
About The Role
We are seeking experienced Senior ASIC Designers.
This role demands proven technical expertise in advanced ASIC design flows, and leadership in execution, cross-functional coordination, and final product delivery. You will be part of an early-stage startup working on an exciting product in the Artificial Intelligence/DataCenter space. The work involves learning advanced LLM in modern data centers and applications to design memory acceleration.
This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA.
Essential Duties & Responsibilities
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As part of the Silicon Design Team, responsible for RTL design of IPs, subsystems and SOCs supporting Netpreme's silicon roadmap.
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Provide technical leadership in defining IP/SOC microarchitecture specifications, and design methodologies. Conduct design reviews to ensure adherence to best practices.
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Guide the team in optimizing the design to meet aggressive performance, power and area goals using advanced architectural and design techniques.
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Drive effective and seamless collaboration with partner teams across architecture, verification, physical design, firmware, DFT, and post silicon domains to ensure successful system level functionality.
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Interface with external IP vendors, foundries and EDA tool providers to ensure dependencies and roadblocks are addressed in a timely fashion to support team deliverables.
Qualifications
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Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
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Minimum of 5+ years of ASIC/SOC digital design experience
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Excellent leadership, communication, team building and stakeholder management skills.
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Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
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Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies.
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Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
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Hands-on design experience in one or more industry standards/protocol stacks such as Ethernet, UCIe, UALink etc.