Perception Engineer

Who We Are:

Aurelius Systems is a VC backed defense tech startup building autonomous, edge deployed directed energy systems for counter-UAS. We build laser weapons to shoot down drones.

We're a small team of engineers, former US military operators, and subject matter experts scaling America's directed energy dominance. The first cost effective, reliable and robust laser weapon system.

Our namesake isn't an accident. Marcus Aurelius wrote about doing the work in front of you, every day, without excuses. Henry Ford didn't wait for permission to reinvent manufacturing. That's how we operate — small team, unreasonable output, no hiding behind the unachievable.

In addition to our San Francisco lab, we’ve opened a Detroit manufacturing hub and we field test weekly on our own 400-acre private range.

The Role and Your Impact:

We are seeking a skilled Perception Engineer to join our software team and work on end‑to‑end perception and sensor‑fusion stack. You will develop, train, and deploy vision and sensor based models; manage data pipelines; and enable real‑time detection and tracking for our laser‑based defense system. This role bridges data science, software engineering, and robotics to deliver reliable, high‑throughput perception performance on edge hardware.

What You'll Own:

• Design, train, validate and fine-tune machine‑learning and deep‑learning models (e.g., YOLO, RT-DETR, CNNs) for object detection, classification, and segmentation.

• Integrate and fuse data from multi‑modal sensors (RGB, thermal, LiDAR/ToF, IMU, encoders) to produce robust, real‑time Regions of Interest (ROIs).

• Research, implement, and as-needed develop high and low-level image-processing techniques, such as deconvolution, low SNR detection, and motion-isolation techniques.

• Collaborate with hardware teams to integrate and troubleshoot sensors (global‑shutter and rolling‑shutter cameras, thermal imagers, LiDAR/ToF modules, IMUs) over GigE Vision, USB3 Vision, CAN, SPI, and I²C protocols; develop and debug embedded firmware in C/C++ (or Rust) for microcontrollers (STM32, NXP, TI) and FPGAs using VHDL/Verilog within RTOS environments (FreeRTOS, Zephyr).

• Build scalable data ingestion, labeling, augmentation, and storage pipelines (simulated and field data) ensuring 100k+ labeled frames accuracy.

• Optimize inference frameworks for edge deployment (GPU/FPGA), achieving ≥500 Hz end‑to‑end throughput.

• Develop dashboards and telemetry for drift analysis, hardware health monitoring, performance metrics, and automated retraining triggers.