FPGA Design Engineer

Principal FPGA Design Engineer 
Location: Oxford
Permanent

Oxford Nanopore Technologies: Our goal is to bring the widest benefits to society through enabling the analysis of anything, by anyone, anywhere. 

The company has developed a new generation of nanopore-based sensing technology for faster, information rich, accessible and affordable molecular analysis. 

The first application is DNA/RNA sequencing, and the technology is in development for the analysis of other types of molecules including proteins. 

The technology is used to understand and characterise the biology of humans and diseases such as cancer, plants, animals, bacteria, viruses, and whole environments. 

With a thriving culture of ambition and strong innovation goals, Oxford Nanopore is a UK headquartered company with global operations and customers in more than 125 countries.

We are seeking a Principal FPGA Design Engineer to own the architecture and technical delivery of the FPGA subsystem for a high-throughput nanopore sequencing platform. 

In this hands-on technical leadership role, you will set the technical direction and guide the engineering team while taking designs through the full lifecycle—from initial requirements and architecture through RTL implementation, custom-ASIC bring-up, lab validation, and product release. 

Note: This is a technical leadership and mentorship role without direct line-management responsibilities. 

Key Responsibilities

• System Architecture: Define and lead the FPGA architecture for our high-throughput sequencing products. 
• RTL Design & Verification: Design and implement digital RTL using SystemVerilog, Verilog, or VHDL on AMD/Xilinx FPGAs. Build simulation testbenches and automated verification environments using tools like Questa or Vivado Simulator. 
• Optimization: Optimize designs for high-speed data paths, throughput, power, timing closure, and resource utilization. 
• Cross-Functional Integration: Collaborate closely with ASIC, hardware, firmware, and software teams to ensure seamless component integration and support custom-ASIC bring-up. 
• Best Practices & CI/CD: Drive best practices in Git-based version control, continuous integration (CI), automated regression, and reusable IP development. 
• Mentorship & Planning: Provide technical guidance and mentorship to FPGA and hardware engineers while contributing to project planning, risk assessments, and development schedules.