Formal Verification Engineer

This role is for one of the Weekday's clients

Salary range: Rs 500000 - Rs 2200000 (ie INR 5- 22 LPA)

Min Experience: 3+ years

Location: Bengaluru, Karnataka, India
JobType: full-time

We are looking for a skilled Formal Verification Engineer to join our SoC verification team and ensure the correctness, robustness, and reliability of complex digital hardware designs using advanced formal verification methodologies. In this role, you will collaborate closely with RTL designers, design verification engineers, and architects to validate critical SoC components throughout the development lifecycle. If you have strong expertise in formal verification, CDC/RDC analysis, and SystemVerilog Assertions, this is an excellent opportunity to contribute to cutting-edge semiconductor products.

Requirements

Key Responsibilities

• Develop, maintain, and execute formal property checks, including assertions, assumptions, and coverage, for complex SoC components such as interconnects, memory subsystems, power management, and security IPs.
• Perform block-level and chip-level formal verification using industry-standard formal verification tools.
• Collaborate with RTL and design verification teams to debug counterexamples, resolve design issues, and achieve formal verification closure.
• Define and enhance formal verification methodologies, reusable verification frameworks, and best practices across projects.
• Contribute to verification planning, coverage analysis, closure tracking, and tape-out sign-off activities.
• Identify RTL design bugs through formal analysis and provide effective root-cause analysis.
• Drive the adoption of Formal Property Verification (FPV), Sequential Equivalence Checking (SEC), connectivity verification, and other advanced verification techniques.
• Own Clock Domain Crossing (CDC) verification by identifying synchronization issues, validating multi-bit crossings, and ensuring safe clock domain interactions.
• Own Reset Domain Crossing (RDC) verification by validating reset synchronization, deassertion sequencing, and eliminating reset-related functional issues.
• Perform structural and formal CDC analysis to verify synchronizer implementation, reconvergence, asynchronous FIFOs, handshake protocols, and Gray-code based crossings.
• Conduct RDC analysis to verify proper reset synchronization, glitch-free reset deassertion, reset sequencing, and reset domain isolation.
• Use industry-standard CDC/RDC verification tools to perform automated analysis, document waivers where required, and drive closure before tape-out.