DFT Engineer

Ricursive Intelligence is a frontier AI lab building self-improving systems, starting with chip design. We are reinventing chip development and closing the loop between AI and the hardware that fuels it, recursively accelerating the path to artificial superintelligence. Backed by $335M from Sequoia, Lightspeed, DST, and NVIDIA Ventures, we are a growing, fast-paced team where every hire shapes the work.

The company has unmatched talent density, including IMO, IPHO, and IOAA gold medalists, pioneers who made prior breakthroughs in chip design: AlphaChip (Nature 2021), ePlace (DAC Best Paper Nominee 2014), RL-CCD (DAC Best Paper 2023), INSTA (DAC Best Paper 2025), and C3PO (ASP-DAC Best Paper 2026), chip leads for Apple Silicon (multiple generations of iPhone and iPad) and Google (TPU, OpenTitan), and top researchers and engineers from Anthropic, Google DeepMind, Stanford, and MIT.

ABOUT THE ROLE

A self-improving chip design system is only as good as the silicon it produces, and silicon only counts once it has been tested, screened, and shipped. We are hiring a DFT engineer who treats testability as a first-class design discipline: someone who has architected the scan, MBIST, and boundary-scan infrastructure for complex chips at advanced nodes, generated and signed off the patterns that qualified them, and then stood at the tester when first silicon came back. Your expertise will teach our systems how to reason about test coverage, test cost, and yield, and you will use those systems to build real silicon.

You will own DFT end to end at Ricursive: DFT architecture and insertion, MBIST planning, fault-model analysis, and ATPG signoff in pre-silicon, then hands-on CP, FT, and SLT bring-up with our foundry and OSAT partners in post-silicon. You will work shoulder to shoulder with the RTL, DV, and physical design engineers, flex into RTL and DV work when the program needs it, and bring AI tools into the traditional DFT flow wherever they make the work faster or the silicon better. As part of a small team, you will have the opportunity to define our foundational DFT methodology and infrastructure from the ground up.

WHAT YOU WILL DO

• Own DFT architecture and insertion for complex silicon at advanced nodes: hierarchical scan and compression, BIST, MBIST and BISR planning and repair, boundary scan, and IJTAG networks (IEEE 1149.1, etc), integrated with the synthesis, physical design, and STA flow from RTL to GDS.

• Define the fault-model and coverage strategy (stuck-at, transition, path-delay, cell-aware, and bridging) and own ATPG generation, fault simulation, coverage closure, pattern verification in zero-delay and SDF gate-level simulation, and DFT signoff to tapeout, making explicit tradeoffs between coverage, test time, pattern count, and area.