Physical Verification Engineer

ABOUT THE ROLE

As a Sr Staff / Principal Physical Verification Engineer, you will be the technical owner of all signoff physical verification activities across advanced process nodes. You will lead DRC, LVS, and DFM sign-off at chip top level, drive hierarchical verification strategies, and own bump planning and package-level DRC across Intel, TSMC, Samsung, and GlobalFoundries technologies spanning 28nm through 2nm. You will be a partner with physical design, package engineering, and foundry teams to ensure first-pass tape out success on chiplet-based products.

KEY RESPONSIBILITIES

Signoff Physical Verification — Top Level

• Own end-to-end physical verification signoff strategy from block level through chip top, ensuring all DRC, LVS, ERC, and antenna violations are cleanly resolved before tapeout.
• Define and execute hierarchical DRC methodology across multiple abstraction levels (block, partition, top), leveraging Calibre or IC Validator in hierarchical and distributed modes.
• Drive full-chip DRC convergence across advanced nodes including 28nm, 22nm, 14nm, 7nm, 5nm, 3nm, and 2nm at Intel, TSMC, Samsung, and GlobalFoundries.
• Develop waiver management processes with foundry sign-off teams; distinguish hard violations from soft DFM advisories and document justifications for each waiver class.
• Collaborate with physical design teams on real-time DRC closure, guiding routing rules, spacing constraints, and metal fill strategies to minimize violations upstream.
• Lead bump planning for flip-chip and 2.5D/3D chiplet assemblies — define bump array configuration, pitch, UBM sizing, and RDL routing to satisfy both electrical and mechanical requirements.
• Execute top-level bump DRC checks including bump pitch, clearance, RDL spacing, keep-out zones, and passivation opening rules per foundry and OSAT PDK requirements.
• Validate bump-to-bump, bump-to-signal, and bump-to-power domain spacing across multiple power domains and IO ring configurations.
• Collaborate with package and substrate teams on co-design constraints to align die-side bump map with package-side ball grid array (BGA) and interposer routing.
• Ensure compliance with electromigration (EM) limits on bump current density and perform IR-drop correlation between die and package.
• Develop and maintain Calibre SVRF/TVF and IC Validator runsets customized per foundry PDK, managing layer name mappings, derived layers, and rule deck versioning.
• Implement incremental and cell-level DRC methodologies to accelerate design iteration turnaround — reducing full-chip DRC runtime by leveraging hierarchical cell reuse.