Component Design & Analysis Engineer
US$154,500 – US$198,000 / yr base salary
Posted 6 Oct 2026
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 5+ yrs
- Management level
- Individual contributor
- Employment
- On-Site
- Contract
- Full-time
| Base salary | US$154,500 – US$198,000 / yr |
|---|
Field of studyElectrical Engineering, Mechanical Engineering, Physics (or related)
Study levelBachelor's or higher
HRL Laboratories, an IBM company, pioneers the next frontiers of physical and information science. Delivering transformative technologies in automotive, aerospace and defense, HRL advances the critical missions of its customers to help them remove limitations and create competitive advantage. HRL then transitions the work back to customers – ready for real-world application. For more than 70 years, HRL’s rich portfolio of scientific discoveries and engineering innovations continues to build on each other — often in unexpected, profound and far-reaching ways. As a private company owned by IBM, HRL prioritizes purpose over profit, significantly advancing the state of the art.
Qubit Systems Laboratory (QSL) is a world leader in semiconductor spin qubits. Our broad expertise spans semiconductor growth, device design and modeling, cryogenic control, high-density interconnects and packaging, quantum architecture, and multiqubit demonstrations. Our system architecture is built entirely around scalable semiconductor manufacturing to make quantum computing affordable for practical business and scientific applications.
General Description
The Integration Component Design and Analysis Engineer will develop interconnect and integration component architectures, perform high level designs and trade space analyses of alternatives, analyze RF and transmission line behavior including complex crosstalk and multi-conductor modal propagation behavior, and collaborate closely with foundry, packaging, and test teams to ensure robust integration and manufacturability in support of HRL’s silicon spin quantum computing efforts. This role requires strong communication skills, deep familiarity with superconducting foundry processes, and the ability to model and analyze RF structures in cryogenic environments. The ideal candidate combines hands on design expertise with an understanding of materials interactions, process constraints, and superconducting test methods that inform design choices and development strategy.
Essential Duties
• Design, analyze, and refine superconducting and non-superconducting component structures—including packages, connectors, transmission lines, RF interconnects, and process dependent device geometries—ensuring compatibility with foundry capabilities and cryogenic requirements.
• Perform RF simulation and analysis of superconducting transmission lines using industry standard tools, evaluating impedance, loss mechanisms, dispersion, crosstalk, and parasitic behavior.
• Collaborate with other team members to precisely characterize components, and validate component performance and characteristics against requirements
• Incorporate deep knowledge of foundry processes, materials interactions, and interface behaviors into component and system level design choices.
• Serve as a key contributor to foundry related problem solving, supporting process development strategies in schedule constrained environments and advising on manufacturable design approaches.
• Apply familiarity with superconducting test methods and relevant theory to guide design decisions, interpret test data trends, and support development planning.
• Collaborate closely with integration, packaging, test, and process engineering teams to ensure alignment across design intent, fabrication capability, and system requirements.
• Document design methodologies, assumptions, simulation models, and validation outcomes; contribute to internal reviews and cross functional technical discussions.
• Communicate technical findings, risks, and recommendations clearly to senior management while providing coordinated guidance to peer engineering teams.