Physical Design Engineer
US$180,000 – US$280,000 / yr base salary
Posted 10 Jun 2026
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 7+ yrs
- Management level
- Individual contributor
- Employment
- On-Site
- Contract
- Full-time
| Base salary | US$180,000 – US$280,000 / yr |
|---|
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.
This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.
About The Role
Join our close-knit physical design team where you will drive high-impact PPA strategy—actively shaping power, performance, and area tradeoffs in direct collaboration with the RTL team. You will excel in and own all disciplines of physical design and implementation from RTL to tapeout, ensuring your blocks integrate seamlessly into our full-chip architecture.
Skills & Qualifications:
Required:
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7+ years of physical design & physical verification experience.
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Strong knowledge of block level and full-chip physical verification methodology.
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Strong experience in block/subsystem timing closure.
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Expert at optimizing for the best power/performance and area.
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Experience with the complete physical design flow.
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Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues.
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Expert with IR/EM analysis and resolution.
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Strong background in STA, constraint drafting and timing convergence at block, partition and fullchip.
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Should demonstrate and raise the bar for “ownership”, “deep dive” and should demonstrate strong fundamental understanding of PD concepts.
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Good understanding of full chip floor planning and integration.
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Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements.
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Demonstrated ability to work with RTL teams to optimize for physical design.
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Skills in Design Compiler, Fusion Compiler, ICC2 or similar physical design tools.