ASIC RTL Design Engineer
US$200,000 – US$290,000 / yr base salary
Posted 7 Oct 2026
Advertised as “Senior ASIC RTL Design Engineer, AI Hardware”
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 8+ yrs
- Management level
- Individual contributor
- Employment
- Hybrid
- Contract
- Full-time
| Base salary | US$200,000 – US$290,000 / yr |
|---|
Field of studyComputer Science, Electrical Engineering (or related)
Study levelMaster's
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.
This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.
About The Role:
As a senior front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.
Responsibilities:
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Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
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Work closely with PD team members for design closure to meet PPA goals.
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Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
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Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
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Debug silicon-level functional, timing, and power issues during bring up.
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Requirements
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Master’s degree in Computer Science, Electrical Engineering, or equivalent.
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Can work in a hybrid work environment.
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8+ years of experience in delivering complex, high performance high quality RTL designs.
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Experience with Front End Chip integration and third-party IP integration.
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Demonstrated experience in high-performance computing, GPU/CPU designs, machine learning or related fields.