Design Verification Engineer

Job Description
Picture yourself developing advanced electronic systems deployed to protect members of our armed services on some of the nation's most sophisticated aircraft. Pretty rewarding, right? And now imagine doing that job while working in a fast-paced environment using state-of-the-art tools and methodologies, all the while increasing your knowledge, growing your skills, and advancing your career.

BAE is looking for experienced FPGA Design Verification Engineers who can develop and use verification environments. Candidates will be given the opportunity to contribute to the evolution of the company's verification processes and methodologies.

While in this job you will

• Develop, and use configurable, self-checking testbenches implemented in SystemVerilog/UVM and/or VHDL;
• Develop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functions in Electronic Warfare systems;
• Collect and analyze coverage metrics, then use that information to improve the effectiveness of testcases;
• Create reusable Verification IP to be shared across the organization;
• Contribute to the evolution of our processes and methodologies.
• Enhance your DV skills as well as your knowledge of Electronic Warfare while working with subject matter experts;
• Work with engineers across multiple U.S. locations

BAE Systems offers competitive pay, benefits, and important work-life balance initiatives including every other Friday Off, Flextime, and Telecommuting. BAE also believes in a culture of recognition for the extraordinary contributions of our skilled employees.

Because of the need for consistent, in-person collaboration and/or the requirement to perform all work onsite due to the nature of this particular role, it will be performed full-time on site.

Required Education, Experience, & Skills

• Bachelor's Degree and 4 to 6 years work or equivalent experience
• Experience developing, and using constrained random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL
• Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence)
• Proven track record of executing to schedule, and driving tasks to closure. Candidates should also be comfortable multitasking because they may be asked to support multiple projects.
• Strong communication and documentation skills
• Experience implementing test plans.
• Ablilty to work effectively in a multi-site or borderless environment

Preferred Education, Experience, & Skills The following skills/experience are preferred, but not required: