FPGA Digital Design Engineer

Job Description
BAE Systems has an open position for a Senior FPGA Digital Design Engineer!

See what you’re missing. Our employees work on the world’s most advanced electronics – from detecting threats for F-35 pilots to illuminating the night for soldiers. Spanning air, land, sea, and space, we are developing the technology of tomorrow, delivered today. Drawing strength from our differences, we’re innovating for the future. And you can, too. Our flexible work environment provides you a chance to change the world without giving up your personal life. We put our customers first – exemplified by our mission: “We Protect Those Who Protect Us®.” Sound like a team you want to be a part of? Come build your career with BAE Systems.

At BAE Systems, we deliver a full range of products and services for air, land and naval forces, as well as advanced electronics, security, information technology solutions and customer support services. If you are an individual that enjoys a cohesive team environment and is interested in a variety of challenges across a variety of products, then we are interested in hearing from you!

Countermeasure & Electromagnetic Attack Solutions (CEMA) Hardware Engineering Group is looking for a Senior FPGA Digital Design Engineer to support FPGA designs through all phases of development. The ideal candidate is expected to perform activities including assisting in design architecture, ownership of RTL coding, synthesis, place and route, timing closure, basic test bench development, lab testing, product support and FPGA security.

Required Education, Experience, & Skills

• Current Security Clearance (Secret), or eligible to obtain one
• Typically 2 of years of relevant experience with bachelor’s degree, or equivalent experience
• Experience in FPGA or ASIC Design / Development, including
  • VHDL (preferred) or Verilog HDL coding
  • Experience with digital design tools and simulators
  • Experience with clock domain crossing techniques
  • Experience with designer-level test bench (VHDL, Verilog, or SystemVerilog)
  • Familiarity with revision control (GIT, CVS, Clearcase, Subversion, etc.)
  • Familiarity with static timing analysis tools and timing closure
  • Working knowledge of internal logic analyzer (ILA/chipscope/signaltap)
• Strong written and oral communication skills
• Self-starter and a good team player
• Ability to mentor and willingness to be mentored
• Strong debug and problem solving skills
• Lab testing support

Preferred Education, Experience, & Skills