Communication Bus Engineer
Posted 28 Apr 2026
Advertised as “RT Communication Bus Engineer (human)”
BranchFactor Summary
The original posting with the fluff stripped out
- Management level
- Individual contributor
- Employment
- On-Site
- Contract
- Full-time
No salary listed for this role.
Field of studyRelevant Field (or related)
Study levelBachelor's
Your mission & challenges
We are growing our real-time communication capability across NEURA's current and next-generation robot platforms. This role owns the deterministic bus layer that connects the robot's real-time operating system to actuators, sensors, and the higher-level Robot Abstraction Layer — EtherCAT, PTP / gPTP, TSN, and CANfd.
You will sit between the kernel and BSP layer (where the RT & Kernel engineer owns OS scheduling and the kernel network path) and the Robot Abstraction Layer (which consumes the bus through a stable communication interface), and collaborate closely with low-level control, hardware, and safety stakeholders to deliver a communication stack that is reliable, measurable, and suitable for a controlled product lifecycle.
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EtherCAT master stack configuration and maintenance for every robot platform: cycle management, slave topology, and integrity monitoring under real workload.
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The real-time communication server that bridges the EtherCAT master to the Robot Abstraction Layer's communication interface — and its evolution as platforms and drives change.
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Servo drive bring-up and commissioning at the firmware / protocol level: drive parameterisation, CoE / SoE handling, fault and state-machine behaviour on real hardware.
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Hardware clock synchronisation (IEEE 1588 PTP, 802.1AS gPTP) and TSN traffic shaping (802.1Qbv/Qav/AS) for deterministic Ethernet on robot cells; RT network path tuning to match.
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CANfd internal bus on the Compute Unit: PHY configuration, bit-timing, frame handling, and bus-level diagnostics.
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Co-review of WCET budgets and cycle timing with the RT & Kernel engineer at the OS / fieldbus boundary, ensuring scheduling, interrupt, and synchronisation assumptions hold under load.
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Measurement and diagnostic tooling for RT communication integrity (latency, jitter, missed cycles), giving dependent teams a shared, evidence-based view of timing.
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Safety- and certification-relevant design participation, documentation, and traceability for the communication path; technical documentation kept current for the wider engineering organisation.
What we can look forward to
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Hands-on experience with industrial EtherCAT master stacks (open-source or commercial) on real hardware — not configuration only.
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Servo drive commissioning experience using EtherCAT-based protocols (CoE / CANopen over EtherCAT, SoE / Sercos over EtherCAT), including drive parameter handling and state-machine debugging.