ASIC Verification Engineer

At Atom Computing, we build quantum computers using arrays of optically trapped neutral atoms that will empower customers to achieve unprecedented computational breakthroughs. Join a world-class team of scientists, engineers, and business professionals to advance the state-of-the-art in quantum computing.

Atom Computing is seeking a Principal ASIC Verification Engineer to lead functional verification of ASICs used in our quantum computer. You will guide test-plan execution across engineers and contractors and contribute directly to testbench development, evaluation, and debug.

Responsibilities

• Own block-to-chip verification plans, schedules, and signoff criteria; lead test development and execution.
• Provide technical direction, mentor engineers, review test plans and code, and participate in candidate interviews.
• Define contractor scope, milestones, and acceptance criteria; review deliverables and oversee integration and handoff.
• Develop Python testbenches, reusable drivers, monitors, reference models, and scoreboards integrated with RTL simulators.
• Implement tests, automate regressions, debug failures, and close coverage. Communicate verification status, unresolved defects, and tapeout risks.
• Lead post-layout gate-level verification, including netlist preparation, SDF annotation, and timing-accurate simulation.
• Verify test modes and patterns with DFT, design, and physical design teams; resolve timing and signoff issues.
• Resolve requirements and interface issues with architecture, RTL, firmware, and hardware teams; support silicon bring-up and validation.
• Perform other duties as assigned.

Experience & Education

• Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent experience.
• 10+ years of ASIC/SoC verification experience, with 15+ preferred.
• Experience verifying multiple ASICs through tapeout and subsequent silicon evaluation, applying findings to improve verification.

Qualifications

• Experience with block-to-chip verification of registers, data paths, and firmware interfaces.
• Strong Python skills for reusable, object-oriented testbenches with constrained-random stimulus, simulation control, checkers, and coverage.
• Ability to build behavioral models of mixed-signal blocks, including their digital interfaces and timing.
• Experience turning design requirements into verification plans, writing SystemVerilog assertions, and closing functional and code coverage.
• Hands-on post-P&R experience preparing netlists and cell/memory models, annotating SDF, and debugging timing simulations.