Digital Design Engineer
US$185,000 – US$230,000 / yr base salary
Posted 14 Sep 2026
Advertised as “Principal/ Sr.Principal Digital Design Engineer ”
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 10+ yrs
- Management level
- People management
| Base salary | US$185,000 – US$230,000 / yr |
|---|
Field of studyElectrical Engineering (or related)
Study levelBachelor's
Field of studyElectrical Engineering (or related)
Study levelMaster's
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Principal Digital Design Engineer:
Role Overview
Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.
This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers.
Key Responsibilities
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Design Ownership & Execution
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Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
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Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance
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Drive designs to production, ensuring accountability for quality, schedule, and overall design success
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Verification & Integration
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Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues
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Own third-party IP integration and block-level verification through sign-off
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Work closely with post-silicon teams to facilitate silicon bring-up and debug
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Technical Leadership