Technologist
US$205,000 – US$255,000 / yr base salary
Posted 18 May 2026
Advertised as “Senior Principal Technologist – Memory”
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 10+ yrs
- Management level
- Individual contributor
| Base salary | US$205,000 – US$255,000 / yr |
|---|
Study levelMaster's or higher
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Are you passionate about pushing the boundaries of system, memory, software, and chip architecture? Do you thrive when pitching cutting-edge technology solutions to customers and industry partners? We are seeking a creative customer facing Technologist to help facilitate Astera’s development of data center memory solutions. In this role, you will play a pivotal role in driving the architecture and definition of future products by leveraging your expertise in system architecture, SOC memory sub-system architecture, PCIe/CXL technologies, DRAM/memory architecture, and hardware-software co-design. You will have the opportunity to directly engage with customers, influence product features and roadmap, and help drive innovation to better solve our customers’ bottlenecks in hyperscale data centers.
This role is fully in person, in San Jose. Some travel may be required.
Basic qualifications
- BS in Electrical or computer engineering, MS or PhD preferred.
- ≥10 year’s experience developing memory-related solutions and integrating them into systems/racks for data centers
- Deep experience with PCIe 5/6, and CXL including protocol level depth
- Expertise in OS software integration including memory allocation/management
- Recent experience with silicon architecture and development especially SOCs with memory controllers (DDR*, LPDDR*, HBM, etc)
- Deep expertise and understanding of memory components (DRAM, etc)
- Strong understanding of datacenter system architecture and design challenges
- Strong understanding of “full stack” solutions from silicon to application integration
- Experience working in a customer-facing role with the ability to articulate technical concepts, influence decision-making, and build business cases
- Ability to dig deeply into technical challenges and use cases