Program Manager, ASIC Design

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

As a Sr. Principal Program Manager, ASIC Design at Astera Labs, you will own the cross-functional execution framework for advanced ASIC programs from early planning through tapeout. You will drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams.

You will partner closely with architecture, RTL design, functional verification, emulation, DFT, synthesis, physical design, CAD, IP, product management, engineering leadership, and external partners.

This is a high-impact role for a technical program leader who can operate in a fast-moving environment, manage ambiguity, drive accountability, and establish scalable execution practices across complex silicon development programs.

Key Responsibilities

• Program Execution & Planning

  • Lead pre-silicon execution of complex ASIC and subsystem programs from concept through tapeout.
  • Own program plans, schedules, milestones, dependencies, risk registers, dashboards, and executive-level status reporting.
  • Drive pre-silicon and NPD phase-gate execution from kickoff through final GDS handoff, ensuring cross-functional readiness across architecture, RTL, verification, DFT, physical design, signoff, and tapeout.

• Cross-Functional Alignment & Coordination

  • Drive cross-functional alignment across architecture, RTL design, verification, emulation, DFT, synthesis, physical design, CAD, IP integration, product management, and external partners.
  • Track IP delivery, PDK updates, CAD/EDA flow readiness, tool dependencies, and foundry requirements.
  • Partner with Post-Silicon PM and Validation teams to absorb feedback from post silicon bring up, including bug reports and Si issues.