SoC Power & Performance Architect

Company Overview

Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.

We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.

If that's you, join us — the intelligence everywhere revolution starts here.

Ambiq is looking for a Sr. Staff SOC Power & Performance Architect to help shape the architecture behind some of the industry’s most power-efficient SoCs. You will drive power and performance analysis, budgeting, modeling, and debug from early architecture through silicon correlation, while defining practical architecture guidance for power management, clocking/reset, fabric, and embedded system behavior.

This role is ideal for a senior low-power SoC architect who enjoys hands-on analysis, silicon debug, architecture specification, automation, and customer-facing technical influence.

Responsibilities 

• Execute power and performance analysis across pre-silicon modeling, RTL power analysis, power-aware simulation, and post-silicon correlation.
• Build and maintain SoC, subsystem, and use-case-level power budgets.
• Drive variance analysis against power and performance targets, surfacing risks early.
• Lead architectural debug of power anomalies in simulation, emulation, or silicon.
• Trace issues from waveform to RTL to architectural intent to root cause.
• Develop and automate power modeling infrastructure, reporting flows, regression dashboards, and analysis tooling using Python and/or TCL.
• Characterize power states, transitions, leakage/dynamic splits, Vmin behavior, retention, and corner behavior on first silicon.
• Feed silicon learnings back into next-generation architecture.