Standard Cell Design Engineer

Who We Are (video)

At JRC, we tackle some of the toughest challenges faced by the Department of Defense (DoD) and other government agencies. Our expertise in engineering innovation and semiconductor technologies allows us to deliver mission-critical microelectronics solutions, aerospace systems engineering, and cutting-edge research and development. By joining JRC, you’ll be part of a team that supports strategic deterrence and defense missions, playing a crucial role in ensuring the safety and security of the United States and its allies.

🚀Join JRC's Semiconductor Technology Team!

Join JRC’s cutting‑edge Semiconductor Technology team as a Senior Standard Cell Design Engineer and lead the development of next‑generation radiation‑hardened microelectronics. In this high‑impact role, you’ll drive the technical execution of our LEAP Standard Cell Library, shape proprietary simulation tools for radiation‑induced reliability prediction, and collaborate closely with foundry partners on advanced-node designs.

You’ll architect and validate new standard cells across multiple technologies, optimize PPA under extreme conditions, support MPW test‑chip runs, and advance key automation and modeling capabilities. This role is ideal for an engineer who thrives at the intersection of device physics, circuit design, and reliability modeling.

We’re looking for someone with deep semiconductor design expertise, hands‑on experience in standard cell and library development, strong simulation and characterization skills, and eligibility for a U.S. security clearance. Experience with advanced nodes, RHBD techniques, memory design, and characterization tools is a strong plus.

If you’re excited about building resilient microelectronics that power mission‑critical systems, we’d love to meet you.

💼What You'll Do

• Execute the design and development of Radiation Hardened LEAP Standard Cell Libraries across multiple advanced foundry technology nodes.
• Generate and validate new standard cells and IP, including combinatorial logic, sequential logic, and power management cells.
• Leverage in-house software and industry-standard SPICE tools to calculate radiation-induced error rates to ensure circuit resilience.
• Execute advanced library characterizations to optimize Power, Performance, and Area (PPA) in harsh environments.
• Collaborate directly with external foundry partners on Multi-Product Wafer (MPW) runs and provide technical design support to customers.