FPGA Engineer
Posted 26 May 2026
Advertised as “FPGA Engineer ”
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 3–6 yrs
- Management level
- Individual contributor
No salary listed for this role.
About Eridan
At Eridan we believe in the power of collaboration and communication to achieve our mission: connect the planet to empower a sustainable, shared future. That mission is possible with our patented transmitter which decreases the cost and power required to roll out 5G by 10x when deployed globally. Learn more about our mission here.
About this Job
We are seeking a Mid-Level FPGA Engineer to join our team and contribute to the development and evolution of our Open RAN Radio Unit (RU) platform. This role is ideal for someone who combines solid FPGA expertise with a strong understanding of digital signal processing and compute architectures, particularly in AI-driven systems.
Responsibilities
- Design, develop, and integrate FPGA-based solutions for Open RAN Radio Units.
- Implement and optimize digital signal processing (DSP) algorithms for high-performance compute applications.
- Work with Xilinx (AMD) FPGA technologies, including Zynq-based platforms; Versal experience is a plus.
- Integrate and validate designs using Vivado, ensuring timing closure, proper routing, and backend implementation correctness.
- Collaborate with system and software teams to translate algorithmic requirements into efficient hardware implementations.
- Contribute to feature development and enhancements of existing ORAN RU products.
- Participate in board bring-up, debugging, and hardware validation processes.
- Analyze and troubleshoot performance bottlenecks across FPGA and system-level designs.
Requirements
- 3–6 years of experience in FPGA design and development.
- Strong understanding of digital signal processing (DSP) concepts and their hardware implementation.
- Solid knowledge of compute architectures and interest in AI/ML acceleration on FPGA.
- Hands-on experience with Xilinx (AMD) tools and platforms, especially Vivado and Zynq.
- Experience with good digital design principles and practices for RTL design (VHDL/Verilog/SystemVerilog) and simulation workflows.
- Familiarity with timing closure, synthesis, and place-and-route processes.
- Comfortable working with hardware debugging tools and board bring-up procedures.
- Experience with Siemens Questa simulation tools.
- Experience with Git, GitHub and general principles of Continuous Integration process.