Design Verification Emulation, Hardware

At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.

Who we are

We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.

About the Role

We are seeking an emulation-focused design verification engineer to drive IP and SoC verification on emulation platforms. Working with simulation-based DV teams, you will translate architectural and microarchitectural definitions into workloads suited to emulation, then adapt and run those tests. You will partner with DV block owners on debug and emulation-specific closure, providing emulation signoff as an input to overall verification signoff. You will also develop the models and infrastructure needed to support this work.

What You’ll Do

• Verification Strategy & Planning: Translate IP and SoC verification plans into execution strategies, mapping tests to simulation, simulation acceleration, or emulator-hosted verification based on runtime, fidelity, and debug needs. Define emulation workload goals and run acceptance criteria with DV block ownersEmulation Models: Build and maintain models and test components for simulation acceleration and emulator-hosted verification flows, balancing fidelity, performance, and debug visibility.
• Emulation Infrastructure: Develop and improve platform bring-up, compile, mapping, runtime, regression, and debug flows.
  Testbench and Workload Development: Adapt or develop test environments, transactors, stimulus, and software-driven workloads that run effectively on emulation platforms.
• Emulation Closure and Signoff: Track workload execution and failures, review results with DV block owners, and help close emulation-specific gaps. Provide emulation signoff as an input to overall IP and SoC verification signoff.
• Emulation Debug and Collaboration: Triage emulation compile, runtime, and test failures; use traces, waveforms, and platform diagnostics to isolate design, model, testbench, or infrastructure issues; partner with RTL and DV block owners to resolve them.
• Agentic AI for Emulation: Build and apply agentic workflows across workload planning, model and test preparation, platform setup, run orchestration, failure triage, result analysis, and closure reporting, improving engineering throughput while keeping results traceable and reviewable by DV owners.