Physical Design Engineer
Posted 1 Oct 2026
Advertised as “AI Silicon, Physical Design Engineer”
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 10+ yrs
- Management level
- Individual contributor
- Employment
- Remote
No salary listed for this role.
Field of studyComputer Engineering, Electrical Engineering (or related)
Study levelBachelor's or higher
About Unconventional
Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand for computation—a demand that is now fundamentally limited by energy, not just in the datacenter, but at a global scale.
At Unconventional, our mission is to solve this. We are rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient. We're doing this by exploiting the rich physics of semiconductors, mapping neural networks directly to the device physics rather than relying on layers of inefficient abstraction.
The Role
As a Member of Technical Staff, Physical Design Engineer, you will be a foundational member of our multi-disciplinary R&D team. We are looking for individuals who thrive at the intersection of architecture and silicon, turning novel AI concepts into high-performance, energy-efficient hardware.
You will be responsible for the "back-end" realization of our novel computing platform, taking complex digital logic from RTL to GDSII.
Responsibilities
- Full RTL-to-GDSII Ownership: Lead the physical implementation of complex, high-performance blocks and top-level SoC integration. This includes floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and physical verification.
- PPA Optimization: Drive aggressive Power, Performance, and Area (PPA) targets. You will work closely with architects to influence the micro-architecture for better physical routability and timing closure.
- Sign-off & Verification: Own the final sign-off process, including Static Timing Analysis (STA), IR drop analysis (static and dynamic), Electromigration (EM), and Physical Verification (DRC/LVS/ERC).
- Methodology Development: Contribute to the development and automation of our physical design flow. Set best practices for synthesis, formal verification (LEC), and parasitic extraction to ensure first-pass silicon success.
- Cross-Functional Collaboration: Work at the interface of digital and analog design, facilitating the integration of custom analog mixed-signal blocks into the digital fabric.
- Partner Engagement: Work to evaluate potential partners that offer AI tools that could greatly improve chip design efficiency