SerDes Characterization & Post-Silicon Validation Engineer

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.

About the Role 
We are looking for a hands-on Senior SerDes Characterization & Post-Silicon Validation Engineer to bring up, characterize, and validate high-speed SerDes interfaces in complex SoCs.

You will work closely with SerDes/IP, mixed-signal, digital, firmware, SI/PI, package, board, and systems teams to take high-speed interfaces from first silicon through product integration and system-level operation. You will also help build our high-speed test and validation capability from the ground up.

Responsibilities 

• Lead post-silicon bring-up and characterization of high-speed NRZ and PAM4 SerDes, including 112G-class interfaces. 
• Develop and execute electrical characterization plans across lanes, data rates, voltage, temperature, channels, and operating conditions. 
• Characterize TX eye quality, jitter, output amplitude, linearity, equalization, RX sensitivity, BER, bathtub curves, CDR performance, and link margin. 
• Validate TX/RX equalization including FFE, CTLE, DFE, adaptation, and link-training behavior. 
• Perform BER and stress testing across representative and worst-case channels. 
• Debug complex link issues spanning SerDes IP, clocks, power, package, PCB/channel, firmware, and digital logic. 
• Correlate silicon measurements with SerDes models, simulations, and channel/SI analysis.