DFT
Posted 6 Aug 2026
Advertised as “DFT Lead”
BranchFactor Summary
The original posting with the fluff stripped out
- Management level
- Individual contributor
- Employment
- Remote
Compensation
No salary listed for this role.
Role speciality
Design for Test (DFT)System on Chip (SoC) Design
What We’re Looking For:
We’re looking for DFT engineers to contribute to and own DFT efforts for blocks and entire dies on the A-0 and A-1 wafer-scale systems.
Ideal Background:
- Experience leading DFT efforts for multiple advanced node SoC tapeouts
Nice to Have:
- Experience leading DFT efforts for large die area (eg reticle-max) chips
- Experience leading DFT efforts for multi-die/multi-chiplet/MCM designs
- Experience leading DFT efforts for AI accelerator SoCs