Hardware Validation & SI Correlation Engineer

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.

About the Role

SambaNova Systems is redefining what’s possible in AI infrastructure—and the hardware that powers it has to be flawless. As a Senior Hardware Validation & SI Correlation Engineer, you will own the technical bridge between simulation and silicon, ensuring that every high-speed link, control bus, and power rail in our next-generation AI server systems performs without compromise.

This is a high-impact, highly visible role that blends deep Signal Integrity (SI) expertise with rigorous system-level hardware validation. You will work at the frontier of AI compute—validating PCIe Gen5/6, DDR5, and 112G/224G Ethernet interfaces on systems pushing the limits of what data center hardware can do. If you thrive in a fast-paced lab environment, love digging into root cause, and want your work to directly accelerate the future of AI, this role is built for you.

What You’ll Do

SI Modeling & Measurement Correlation

• Drive the correlation between pre- and post-layout SI simulations and physical lab measurements, closing the loop between theory and hardware reality.
• Quantify simulation-vs-measurement gaps for PCIe Gen5/6, DDR5, and 112G/224G Ethernet using S-parameters, TDR, and eye diagram analysis.
• Develop and refine EM models for PCB discontinuities, high-speed connectors, and vias using Ansys HFSS, Cadence Sigrity, or equivalent tools.
• Investigate discrepancies caused by manufacturing tolerances, material properties (Dk/Df), or de-embedding inaccuracies and drive them to resolution.

System-Level Electrical Validation

• Lead validation of housekeeping and control buses—I2C, SPI, eSPI, UART, SMBus—ensuring protocol compliance and robust timing margins.
• Validate complex power-on/off sequences and correlate VR control loop simulations with physical transient response and ripple measurements.
• Ensure reliable operation of sideband signals, reset logic, and BMC hardware interfaces under intensive AI workloads.
• Work cross-functionally with SI, Power Integrity (PI), and Firmware teams to resolve system-hang and link-training failures rooted in electrical noise or power instability.