Post-Silicon Lab Manager

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

To support our next-generation, high-performance RISC-V CPU architectures and advanced chiplet solutions, Tenstorrent is looking for a hands-on, experienced Post-Silicon Lab Manager. In this role, you will own the post-silicon lab infrastructure and manage operational workflows supporting bring-up, system validation, and customer enablement. You will scale the lab infrastructure to support multiple programs with varied requirements. You will direct post silicon validation engineers on cost building cost effective validation and debug infrastructure.

This role is hybrid, based out of Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You hold a B.S. or M.S. in Electrical Engineering, Computer Engineering, or a similar technical field, and you have 8–12+ years in semiconductor hardware, including 3+ years leading a post-silicon validation, characterization, or hardware lab team focused on CPUs.
• You know high-speed interfaces (PCIe, DDR/GDDR/HBM, SerDes) and fabric links in depth, and you're hands-on with board-level debug tools.
• You bring a startup mindset. You stay calm and quick when troubleshooting physical hardware under tight tape-out and silicon-arrival deadlines.
• You communicate clearly across functions and keep remote, multi-site teams aligned from the Santa Clara hub.

What We Need

• Run day-to-day lab operations for CPU post-silicon validation, power/performance assessment, and debug, with lab infrastructure aligned to tape-out and bring-up schedules.
• Lead the lab environment for first-silicon power-on, system bring-up, and platform validation, including board-level fixes to salvage eval boards or meet new validation needs.
• Deploy and maintain server racks, data acquisition, power telemetry rigs, and automated test benches for multi-core CPU and chiplet-based systems. Manage the CapEx budget for scopes, logic/protocol analyzers, and traffic generators.