Silicon Intern

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Overview: This is where verified RTL becomes an actual, manufacturable chip. Every timing constraint, every power tradeoff, every Design For Test (DFT) decision here determines whether the silicon works when it comes back from the fab. 

What you might work on: This posting spans multiple teams within Physical Design and DFT. One application, one recruiter screen — then we match you to the specific team and location that fits best. Team include: 

• Physical Design: Synthesis, floorplanning, place & route, clocking, timing closure.
• Advanced Physical Design: ML-assisted approaches to physical design flows.
• DFT: Design hardware to enable structural post-silicon test. JTAG, Scan/ATPG, MBIST.

This role is on-site, based out of Austin, TX or Boston, MA or Fort Collins, CO or Santa Clara, CA. 

Who You Are

• Currently pursuing a BS, MS, or PhD in Electrical or Computer Engineering, Computer Science, Software Engineering.
• Solid understanding of logic design, VLSI, and transistor-level concepts.
• Familiarity with PnR tools, timing analysis, and power optimization techniques.
• Familiarity with JTAG, MBIST, and scan concepts.
• Comfortable scripting in Tcl, Perl, Shell, or Python.

What We Need

• Hands-on experience with a commercial PnR toolchain (Synopsys, Cadence).
• Coursework or projects in DFT, test methodology, VLSI or digital design, computer architecture.
• Interest or exposure with AI tools to accelerate development and workflows.

What You Will Learn

• The physical design flow, from RTL handoff to final tapeout.
• Timing, power, EM/IR, and area tradeoffs at the chip level.
• Industry-standard EDA tools and flows used in modern chip development.
• Gain hands-on experience in Design-for-Testability (DFT) to enable efficient testing.