Embedded Performance Engineer
Posted 10 Dec 2025
Advertised as “Senior Embedded Performance Engineer”
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 3+ yrs
- Management level
- Individual contributor
No salary listed for this role.
Field of studyComputer Science, Electronic Engineering, Mathematics, Physics (or related)
Study levelBachelor's
About Fractile
Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.
The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.
The Role
On the device, close to the metal, we write the runtime software that orchestrates work across the chip and runs performance-critical ML kernels. This is where performance gets real and the wins compound. Your work directly influences trade-offs for the silicon, system deployment, and the compiler.
You'll drive the first accelerator compute runs, evaluating performance on silicon, running early benchmarks, and feeding results back into the hardware and software roadmap.
What you’ll do
- Write and optimise performance-critical ML kernels in C, with assembly where it matters (RISC-V and our own ISA)
- Build the low-level control paths that feed those kernels, including scheduling, synchronisation, and data movement
- Write targeted validation workloads and microbenchmarks to keep simulation and hardware behaviour aligned and performance measurable.
- Profile, benchmark, and track regressions so performance improvements are real and repeatable
- Work closely with simulation, hardware, ML, compiler, firmware, and runtime engineers in a tight loop, turning profiling data into architecture feedback and real performance wins.
What we’re looking for
- Proven deeply embedded software experience
- Strong performance instincts. You can reason about low-level architecture, memory behaviour, and where the cycles are spent
- Excellent C, and a pragmatic approach to building high-quality, maintainable low-level code