Physical Design Engineer

Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.

We're looking for a Lead Physical Design Engineer to take end-to-end ownership of SOC -top for our next-generation SoCs. This is a hands-on, high-accountability role — you'll be the single point of ownership driving the full chip from block integration through timing, power, signal integrity, and physical closure to tapeout-ready GDS. You'll work closely with block-level PD owners, DFT, package/IO teams, and the architecture team. This role will be in the newly formed hardware engineering group and will focus on designing in state of the art finfet technologies.

This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

• Full-chip integration: floorplanning, power planning, macro/hard-IP placement, and block partitioning at the top level, ensuring convergence across all hierarchical blocks
• Timing closure: full-chip STA across all corners/modes (setup, hold, OCV, multi-mode multi-corner), including cross-boundary timing and chip-level constraint (SDC) ownership
• Power: full-chip power planning, PDN design/analysis (IR drop, EM), rail architecture, and coordination on power-gating strategy with block owners
• Physical verification: DRC/LVS/antenna closure at the top level, seal ring integration, and coordination of ECO cycles across blocks
• Signal integrity & noise: crosstalk, di/dt, and chip-level noise closure, especially around high-speed IO and PLL/analog boundaries
• Clock & reset architecture: top-level clock tree strategy across domains, including CTS coordination with block owners
• DFT integration: chip-level scan stitching, MBIST/JTAG integration, and coordination with DFT lead on ATPG/test coverage closure at full-chip level