Digital Verification Engineer

Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.

We are looking for a senior Digital Verification contractor to take ownership of verification for complex blocks and subsystems in our SoC, including Efficient's proprietary Fabric technology. You will join our newly formed Verification & Emulation team and work directly with RTL designers and architects. We need someone who can ramp quickly on a spec, stand up or extend a UVM environment with minimal direction, and drive it to coverage closure.

Tasks

• Own verification of assigned blocks and subsystems from spec review through coverage sign-off.
• Write verification plans from design and architecture specifications, and review them with design and architecture leads.
• Architect, build, or extend UVM/SystemVerilog testbenches: agents, scoreboards, reference models, sequences, and constrained-random tests.
• Write SystemVerilog assertions and functional coverage models, and drive functional and code coverage to closure.
• Debug complex simulation failures and work with RTL designers to root-cause and fix bugs.
• Report verification status, risks, and coverage gaps clearly to the DV lead and design team.
• Document your environment so it can be handed off to and maintained by the full-time team.

Required qualifications

• Education: Bachelor's or Master's/PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 8+ years of ASIC/SoC design verification, with multiple projects taken from testbench development through tapeout.
• UVM and SystemVerilog: Expert in UVM testbench architecture and SystemVerilog for verification, including classes, constraints, interfaces, functional coverage, and assertions (SVA).
• Coverage closure: A track record of driving functional and code coverage to sign-off on multi-million-gate designs.