Digital Verification Engineer
US$160,000 – US$245,000 / yr base salary
Posted 1 Sep 2026
Advertised as “Staff Digital Verification Engineer”
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 10+ yrs
- Management level
- Individual contributor
| Base salary | US$160,000 – US$245,000 / yr |
|---|---|
| Cash bonus | US$16,000 – US$24,500 |
| Total comp | US$176,000 – US$269,500 |
Field of studyComputer Engineering, Electrical Engineering (or related)
Study levelBachelor's or higher
Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.
We are looking for an experienced Staff Design Verification Engineer to drive the functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team. This is a great opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!
Required Qualifications & Experience
- Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience: 10+ years of progressive experience in ASIC/SoC design verification with multiple full cycles of ownership from testbench architecture through tapeout.
- UVM and SystemVerilog: Expertise in UVM-based testbench architecture and constrained-random verification methodology
- C/C++ experience for modelling or verification.
- Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
- Debug Skills: Proven ability to debug complex simulation failures.
- Scripting & Automation: Proficiency in Python for test automation, log analysis, coverage post-processing, and regression flow development.
- Communication: Ability to clearly communicate verification risk, status and tradeoffs to technical peers and program leadership.
Ways to stand out :
- Experience in Formal verification (JasperGold or similar).
- Experience building or using AI Agentic flows for DV.
- Software/Firmware based testing experience and working with software teams pre-silicon
- Post-silicon experience
- SoC Architecture: Understanding and experience in some of the following areas : processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.