SoC STA Engineer

About InnoPhase IoT

If you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work--not just singing the same song every day, you’ll find your playground at Innophase IoT.

We are looking for people seeking AWESOMENESS! If you’re good at what you do, you can work anywhere. If you’re the best at what you do, come work at Innophase IoT!

Job Summary

We are seeking a highly experienced Senior SoC STA Engineer to own chip-level timing sign-off for next-generation SoC designs. In this role, you will work closely with RTL Design, Physical Design, Architecture, DFT, Verification, Product Engineering, and EDA vendors to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out.

This is a hands-on senior technical role focused on chip-level static timing analysis (STA), timing closure, constraint development, methodology enhancement, automation, and pre-/post-silicon timing correlation.

Key Responsibilities

• Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, process corners, voltage, and temperature conditions.
• Develop, maintain, and validate sign-off-quality SDC constraints for clocks, resets, high-speed I/O interfaces, DFT, and configuration logic.
• Drive timing closure at both block and full-chip levels through critical path analysis, ECO implementation, and close collaboration with Physical Design teams on floorplanning, placement, CTS, routing, and optimization.
• Perform advanced multi-mode multi-corner (MMMC) timing analysis including clock-domain crossing timing, OCV/AOCV/POCV methodologies, and advanced-node timing sign-off.
• Lead signal integrity and crosstalk analysis, identify noise-induced timing issues, and drive mitigation strategies with implementation teams.
• Conduct pre- and post-silicon timing correlation and drive timing sign-off readiness reviews and tape-out closure activities.
• Define and enhance organization-wide STA methodologies, sign-off standards, timing closure best practices, and automation infrastructure.
• Build and maintain STA automation and reporting flows using Python and Tcl for regression tracking, QoR analysis, dashboards, and sign-off reporting.
• Work closely with RTL and System Design teams during early design phases to improve physical awareness and timing convergence.
• Collaborate with cross-functional teams including RTL Design, Physical Design, Verification, DFT, Product Engineering, and Test Engineering to ensure timing requirements are met throughout the design cycle.