Verification Engineer

itD is seeking a Verification Engineer to support the development and verification of next-generation System-on-Chip (SoC) solutions. The ideal candidate will have 5–12 years of design verification experience with expertise in UVM, SystemVerilog, and ASIC/SoC verification, along with a proven ability to deliver high-quality silicon solutions.

Location: 100% onsite in Allentown, PA or Carlsbad, CA.

Pay Rate: PA: $34.00–$34.20/hr | CA: $41.00–$41.40/hr, depending on experience.

We provide comprehensive medical benefits, a 401(k) plan, paid holidays, and more. Please note that we are only considering direct W2 candidates at this time, as we are unable to offer sponsorship.

Responsibilities:

• Develop and maintain UVM-based verification environments for ASIC/SoC designs.

• Create and execute block- and system-level verification plans.

• Design verification components, including assertions, agents, traffic generators, and scoreboards.

• Partner with cross-functional engineering teams to define verification strategies and improve design testability.

• Debug and resolve complex design and verification issues throughout the development lifecycle.

• Perform timing and gate-level simulations to validate design functionality.

• Support post-silicon bring-up through C-based firmware development and verification activities.

Internal Responsibilities:

• Attend regular internal practice community meetings.

• Collaborate with your itD practice team on industry thought leadership.

• Complete client case studies and learning material (blogs, media material).

• Build out material to contribute to the Digital Transformation practice.

• Attend internal itD networking events (in person and virtual).

• Work with leadership on career fast-track opportunities.

Required Qualifications and Skills:

• Bachelor's degree in Electrical Engineering or a related field.

• 5–12 years of ASIC or SoC design verification experience.

• Strong experience developing UVM-based testbenches.