Asic Design Engineer

About Tensordyne

Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different environments with the ability to quickly learn and then solve complex problems. Tensordyne is a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We are at the leading edge of advancing the latest research and product improvements for Al inference solutions that will make Al even more advantageous for compelling new applications. Tensordyne is a well funded, fast-paced startup company with headquarters in both Sunnyvale, CA, and Munich, Germany. We also have many talented team members working remotely. We prioritize our employees' well-being and their families, aiming for a healthier, happier life inside and outside work. We value their contributions and offer tailored benefits for health and financial security, catering to different life stages. Our comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards, reflect our commitment to a supportive and inspiring work environment.

About the role:

As a member of Tensordyne’s ASIC team, you will be responsible for the microarchitecture and design implementation of high-performance AI ASICs. These ASICs closely couple novel computational accelerator units, compute, interconnects, networking and 3rd-party IP blocks as needed to redefine the next generation of tokenomics for inference.

Your responsibilities will be wide-ranging and span at minimum the following:

Responsibilities:

• Work with architecture on reconciling changes with respect to micro-architecture
• Define microarchitecture and document
• Select and integrate 3rd-party IP blocks
• Collaborate with design verification engineers
• Run, analyse frontend synthesis and address all issues
• Collaborate with backend teams on place-and-route guidance and timing closure
• Ability to leverage GenAI usage across all workflows, while retaining ownership and quality of all generated collateral

Required Qualifications:

• 3+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog.
• Experience in IP integration, specifically CPU IP into SoC.
• Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation