Full Chip Physical Verification Engineer

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
• Develop, maintain, and optimize physical verification flows for advanced node SoC’s.
• Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changes
• Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
• Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance
• Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
• Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
• Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows

BASIC QUALIFICATIONS: