Engineer
Posted 16 Oct 2026
Advertised as “Sr Staff Engineer, Program/Project Management- Test Readiness Lead”
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 5+ yrs
- Management level
- People management
No salary listed for this role.
Field of studyComputer Engineering, Computer Science, Electrical Engineering (or related)
Study levelBachelor's or higher
CertificationsSix Sigma Black Belt
Req ID: 141836
Region: Americas
Country: USA
State/Province: Texas
City: Austin
Summary
As the Senior Manager of HPS Test Engineering, you will own the end-to-end testing architecture, strategy, and execution for next-generation or products and infrastructure. This position bridges the gap between top-tier silicon designers, internal hardware/software teams, and volume manufacturing operations. You will be responsible for leading a high-performing team of test hardware and software engineers to develop comprehensive test solutions (ICT, FCT, SLT, BI and Boundary Scan). You will maintain critical cross-functional alignment with the Front-End Senior Manager, Back-End Senior Manager, and Director of Technology Roadmapping to maximize test coverage, minimize escape metrics, and optimize manufacturing throughput and first-pass yield.
Detailed Description
1. People Management & Team Leadership
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Talent Development & Mentorship: Directly manage, coach, and mentor a specialized team of Test Hardware and Software Engineers, fostering technical proficiency in advanced diagnostic test development and automated frameworks.
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Performance Management: Define clear test engineering metrics, KPIs, and deliverables; conduct objective performance evaluations and outline robust engineering career paths.
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Resource Optimization: Plan and manage engineering bandwidth, test equipment budgets (CapEx), and lab infrastructure allocations across concurrent high-visibility NPI initiatives.
2. Early Engagement & Design for Testability (DFT)
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DFT Strategy Ownership: Drive comprehensive DFT/DFx technical reviews during early schematic and board layout design stages to maximize structural and functional test access.
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Silicon Partner Collaboration: Engage directly with tier-1 silicon architects (e.g., Nvidia, Broadcom, Marvell, Intel, AMD) to embed built-in self-test (BIST), high-speed JTAG boundary scan architectures, and advanced custom diagnostic hooks.
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Test Plan Architecture: Formulate unified product test specifications (PTS) defining rigorous test coverage matrices, test point allocations, and optimization bounds before design freeze.
3. Advanced Test Characterization & Process Development
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Oversee the specification, architecture, and deployment of In-Circuit Test (ICT), Functional Test (FCT), System-Level Test (SLT), and Environmental Stress Screening (ESS/Burn-in) solutions.