Principal Design Verification Engineer

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

PRINCIPAL DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Responsible for digital ASIC and/or FPGA verification at block and system level
• Lead and execute verification test plan, development, and milestones from beginning to end
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 10+ years of experience with design verification and test bench development
• 10+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM/OVM/VMM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical milestones

ITAR REQUIREMENTS:

• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.  

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.