Design Verification Engineer
US$150,000 – US$350,000 / yr base salary
Posted 11 Sep 2025
Advertised as “Design Verification Engineer - Interface IP”
BranchFactor Summary
The original posting with the fluff stripped out
- Management level
- Individual contributor
- Employment
- On-Site
- Contract
- Full-time
| Base salary | US$150,000 – US$350,000 / yr |
|---|
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.
Key responsibilities
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End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
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Understand vendor IP configurations and handle handshake with internal IP team
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Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.
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Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.
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Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.
You may be a good fit if you have
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5+ years of design verification experience
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You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.
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You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.
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You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.
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You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.
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You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.
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