Design Verification Engineer
US$185,000 – US$230,000 / yr base salary
Posted 14 Sep 2026
Advertised as “Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet ”
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 10+ yrs
- Management level
- People management
| Base salary | US$185,000 – US$230,000 / yr |
|---|
Field of studyComputer Engineering, Electrical Engineering, Electronics Engineering (or related)
Study levelBachelor's or higher
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Principal / Senior Principal Design Verification Engineer – CXL / PCIe / Ethernet:
Role Overview
We are seeking an experienced Principal / Senior Principal Design Verification Engineer to lead the verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. This is a highly visible technical leadership role where you will define verification strategies, drive methodology improvements, mentor engineering teams, and collaborate across architecture, RTL, firmware, validation, and silicon teams to ensure first-pass silicon success.
The ideal candidate is passionate about building world-class verification environments, has deep expertise in protocol verification, and enjoys solving complex architectural challenges.
Key Responsibilities
Technical Leadership
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Lead the verification strategy for complex IPs and SoC subsystems from architecture through silicon.
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Define verification methodologies, reusable verification frameworks, and best practices across multiple programs.
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Drive verification planning, execution, coverage closure, and sign-off.
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Identify verification risks early and proactively drive mitigation plans.
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Lead technical reviews including architecture, RTL, verification, and tape-out readiness reviews.
Design Verification
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Architect and develop scalable UVM/System Verilog verification environments.
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Develop constrained-random, coverage-driven verification methodologies.
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Design scoreboards, protocol monitors, checkers, assertions (SVA), and functional coverage models.