Microarchitect / RTL Design - Memory Subsystem
Posted 12 Aug 2026
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 5+ yrs
- Management level
- Individual contributor
- Employment
- On-Site
- Contract
- Full-time
No salary listed for this role.
About Architect Labs
Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world.
What You’ll Do
As a Member of the Technical Staff on the RTL Design team at Architect, you’ll own the AI-driven microarchitecture and RTL design of the memory subsystem going into production silicon. You will define, drive, and revise the block-level micro-architecture specification for memory controllers, memory hierarchy management, and memory-side accelerators — ensuring maximum bandwidth utilization, minimal latency, and efficient power delivery for compute-intensive ML workloads.
Core Responsibilities
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Own the memory subsystem RTL end-to-end: from DDR/HBM controller design through code generation, lint, CDC, synthesis, and timing closure using our AI-driven design flow.
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Design and implement memory controllers: including DDR5/LPDDR5X PHY-side controller logic, HBM3/HBM3E pseudo-channel controllers, command scheduling (open-page/close-page policies, bank-level parallelism), refresh management, and ECC/RAS engines.
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Architect the memory hierarchy: including multi-level cache controllers, scratchpad memory managers, coherency protocol engines (where applicable), prefetch engines, and bandwidth partitioning/QoS mechanisms to serve diverse traffic profiles from ML accelerator datapaths.
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Design memory-side accelerators: near-memory compute logic, scatter-gather DMA engines, address translation/remapping units, compression/decompression engines co-located with memory interfaces, and intelligent prefetchers tuned for ML access patterns.
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Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade-offs (bandwidth vs. latency vs. area vs. power), and feed area/timing/power realities back into the architecture and internal AI systems.
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Define and maintain interface specifications: DDR PHY interfaces (DFI), HBM PHY interfaces, on-chip SRAM interfaces, AXI/ACE/CHI for memory-facing fabric ports, and custom interfaces for near-memory accelerator datapaths.