Digital Design Engineer
US$150,000 / yr base salary
Posted 19 Aug 2026
Advertised as “Senior Digital Design Engineer”
BranchFactor Summary
The original posting with the fluff stripped out
- Management level
- People management
- Employment
- Hybrid
- Contract
- Full-time
| Base salary | US$150,000 / yr |
|---|
Field of studyComputer Engineering, Electrical Engineering (or related)
Study levelBachelor's or higher
Senior or Staff Digital Design Engineer
Reports To: Head of Engineering
About Us
Powerlattice is a well-funded semiconductor start-up company backed by leading Silicon Valley venture capital firms. We are developing groundbreaking chiplet power delivery technology that will transform how high-performance processors are powered, enabling the next generation of AI and advanced computing.
About the Role
We are seeking an experienced and hands-on Senior Digital Design Engineer to contribute to the design and implementation of complex digital systems and SoC components. This role offers the opportunity to own significant functional blocks from microarchitecture through RTL development, integration, and implementation while collaborating closely with verification, physical design, and DFT teams.
The ideal candidate is passionate about digital design, enjoys solving challenging technical problems, and thrives in a collaborative startup environment where individual contributions have a direct impact on product success.
Key Responsibilities
Digital Design & RTL Development
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Develop microarchitecture for assigned digital blocks and subsystems
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Design, code, and maintain high-quality, synthesizable RTL
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Evaluate design tradeoffs involving performance, power, area (PPA), and testability
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Participate in design reviews and incorporate feedback into RTL implementation
Integration & Implementation
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Integrate RTL into larger subsystem and SoC environments
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Support lint, CDC/RDC, synthesis, and design quality checks
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Collaborate with physical design teams to resolve implementation issues
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Assist with timing constraint development and timing closure activities
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Support logic equivalence checking (LEC) and implementation debugging
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Participate in functional and timing ECO development when required
Design Quality
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Ensure designs meet functional, timing, power, and DFT requirements
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Support silicon bring-up, validation, and post-silicon debug activities
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Analyze and resolve design issues throughout the development lifecycle
Cross-Functional Collaboration