Design Verification Engineer
US$190,000 – US$230,000 / yr base salary
Posted 4 Jun 2026
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 3–5 yrs
- Management level
- Individual contributor
- Employment
- On-Site
- Contract
- Full-time
| Base salary | US$190,000 – US$230,000 / yr |
|---|
Field of studyComputer Science, Electrical Engineering
Study levelBachelor's or higher
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.
This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.
Key Responsibilities
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Work with architects, designers, post silicon and software engineers to ensure a high-quality design that works for silicon.
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Develop and implement verification strategies, detailed tests and coverage plans based on micro-architecture.
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Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage.
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Implement tests, manage regressions, gather coverage, and debug test failures.
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Collaborate with cross-functional teams including architecture, RTL design, physical design, firmware, and validation.
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Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases.
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Continuously enhances verification infrastructure and flows to improve efficiency and quality.
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Contribute to the evolution of the overall verification methodology and best practices across the organization.
Skills and Qualifications
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Great debugging and problem-solving skills.
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Deep knowledge of SystemVerilog testbench, DPI and UVM.
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Excellent programming skills and knowledge of software engineering practices including object-oriented design.
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Experience developing scalable and portable testbenches and components.
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Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate level simulations.
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Proficient in scripting languages such as Python or Perl.