PCB Layout Engineering
US$210,000 – US$230,000 / yr base salary
Posted 3 Sep 2026
Advertised as “PCB Layout Engineering Lead”
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 10+ yrs
- Management level
- Individual contributor
- Employment
- Remote
- Contract
- Full-time
| Base salary | US$210,000 – US$230,000 / yr |
|---|
Field of studyElectrical Engineering, Electronics Engineering (or related)
Study levelBachelor's
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.
This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.
Cerebras is seeking an exceptional PCB Layout Lead to own the physical implementation of complex, high-performance printed circuit boards for AI systems. This role will translate schematics and engineering requirements into production-ready layouts, optimizing signal integrity, power integrity, thermal performance, reliability, and manufacturability.
Responsibilities
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Own multilayer PCB layout from initial component placement through fabrication and assembly release.
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Translate schematics, mechanical constraints, and electrical requirements into constraint-driven board designs using industry-standard PCB layout tools.
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Define and implement board stackups, controlled-impedance structures, routing rules, reference planes, return paths, and length- and phase-matching constraints.
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Place and route high-speed digital, high-current power, and sensitive analog circuits, including dense BGA fanout and differential interfaces.
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Apply signal-integrity and power-integrity best practices to minimize crosstalk, discontinuities, noise, voltage drop, and electromagnetic interference.
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Collaborate with electrical, SI/PI, mechanical, thermal, compliance, manufacturing, and test engineers to establish constraints and resolve layout issues.
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Work with fabrication and assembly partners to select materials, validate stackups and via structures, and improve yield, cost, and schedule.
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Perform design reviews and DFM, DFA, and DFT checks; generate and verify fabrication drawings, assembly drawings, drill data, Gerbers, ODB++, IPC-2581, and related release packages.
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Maintain component footprints, padstacks, design libraries, layout standards, and release documentation.