Director of 3D Stacked Logic Design

About SK hynix America:

At SK hynix America, we are at the forefront of semiconductor innovation. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers. With major investments in the U.S. and a leading position in the global AI revolution, we build the critical infrastructure of the digital landscape and remain committed to sustainable operations. We invite innovative minds to be part of our journey. Here, you will be part of a collaborative team pioneering the next generation of memory technologies, expanding our market footprint, and defining the future of computing.

Work Model: Onsite

Job Title: Director of 3D Stacked Logic Design
Office Location: San Jose, CA
Job Type: Full-Time
Work Model: Onsite 

Job Summary:

This role leads the design and implementation of high-speed digital IP for 3D-stacked DRAM peripheral circuits and DFT, driving co-development initiatives with U.S.-based customers to enable DRAM-on-Logic system configurations. Key responsibilities include managing foundry verification of service-ready IPs, establishing IP business infrastructure, and ensuring seamless integration within customer design environments. The position focuses on strengthening market leadership through advanced digital IP design and delivering comprehensive services that support the co-design of 3D-stacked DRAM logic dies.

Responsibilities:

• Lead the design of high-speed digital IP for 3D-stacked DRAM peripheral circuits and DFT with U.S.-based customers (including RTL design to implementation).
• Drive foundry Verification of Service-Ready IPs and Infrastructure Setup for IP Business.
• Deliver Services to Ensure Seamless IP Integration in Customer Design Environments.
• Strengthen Leadership in the DRAM-on-Logic Era through advanced digital IP design for 3D-Stacked DRAM.
• Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for customers.
• Co-design of 3D-stacked DRAM Logic Die with U.S –based customers.
• Improve competitiveness through close engagement with customers in US.

Qualifications:

• Bachelor’s degree or higher in Electrical Engineering or a related discipline.
• Development of Digital Logic IP/SoC based on Hardware Description Languages (Verilog, VHDL).
• 8+ years of relevant experience in the following areas:
  • Experience in RTL design and implementation memory PHY, hard macro IP for high-speed circuit, or high-speed digital IP design